Algorithm Level Error Detection in Low Voltage Systolic Array

In this brief an approach is proposed to achieve energy savings from reduced voltage operation. The solution detects timing-errors by integrating Algorithm Based Fault Tolerance (ABFT) into a digital architecture. has been studied with systolic array matrix multiplier operating at voltages, detecting errors on-the-fly avoid demanding memory round-trips. analysis of the done using analog-digital co-simulation extract transient behavior under different voltages and clock frequencies. HSPICE simulations $90nm$ CMOS transistor models, experiments reducing operation FPGA device were carried out. simulations, showed possibility 10x increase in energy-efficiency approaching near-threshold region.